Digilent Genesys2 – Kintex-7 FPGA Development Board

• Digilent Adept USB port for programming and data
• Ten GTX lanes available in the FMC connector
• Micro SD card connector
• Audio codec w/ four 3.5mm jacks
• Serial Flash

Powered by Xilinx’s Virtex-7 XC7V690T FPGA, the NetFPGA-SUME is an ideal platform for high-performance and high-density networking design. 32 GTH serial transceivers have been used to provide access to 8 lanes of end-point PCI-E (Gen3 x8), 4 SFP+ (10Gbps) ports, 2 SATA-III ports (6Gbps), and 18 data-rate-adjustable GTH ports through an HPC-FMC connector and a QTH connector. Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36-bit buses and two 4GB DDR3 SODIMMs with 64-bit buses provide an ideal memory solution for common networking applications.

The Genesys 2 board can receive power from an external power supply through the center-positive barrel jack (J27). The external supply voltage must be 12 V ±5 %. The Genesys 2 cannot be powered from the USB bus. All Genesys 2 power supplies can be turned on and off together by a single logic-level power switch (SW8). Power supplies are either enabled/disabled directly by the power switch or indirectly by other supplies upstream. A power-good LED (LD15), driven by the “power good” output of the on-board regulators, indicates that the supplies are turned on and operating normally. An overview of the Genesys 2 power circuit is shown in the left figure.

The configuration and calibration registers are volatile, so they need to be initialized after power-up. After initialization is done voltage, current, and power values can be read from dedicated registers. It is recommended to add glitch filters to the I2C master controller to avoid spurious start or stop conditions occurring on the bus. This is especially important when using an external I2C master connected to the J18 header (not mounted by default).

After power-on, the Kintex-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of four ways:

• A PC can use the Digilent USB-JTAG circuitry (port J17, labeled “USB JTAG”) to program the FPGA any time the power is on.
• A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA.
• A programming file can be transferred to the FPGA from a micro SD card.
• A programming file can be transferred from a USB mass-storage device (ex. pen drive) attached to the USB HOST port.

The Genesys 2 board contains two external memories: a 1GiByte volatile DDR3 memory and a 32MiByte nonvolatile serial Flash device. The DDR3 uses two 16-bit wide memory components with an industry-standard interface soldered on the board resulting in a 32-bit data bus. The serial Flash is on a dedicated quad-mode (x4) SPI bus.

The Genesys 2 board includes a Realtek RTL8211E-VL PHY paired with an RJ-45 Ethernet jack with integrated magnetics to implement a 10/100/1000 Ethernet port for network connection. The PHY interfaces with the FPGA via RGMII for data and MDIO for management. Bank 33 powered at 1.5V is populated with these signals. The auxiliary interrupt (INTB), power management (PMEB) signals are wired to bank 32 and powered at 1.8V. Both of these signals are open-drain outputs from the PHY and need internal pull-ups enabled in the FPGA, if they are used.

At power-on reset, the PHY is set to the following defaults using the configuration pins in parenthesis:

• Auto-negotiation enabled, advertising all 10/100/1000 modes (AN[1:0])
• PHY address=00001 (PHY_AD[2:0])
• No delay for TXD and RXD relative to TXC and RXC for data latching (RXDLY, TXDLY)

If an Ethernet cable is plugged in, establishing a link is attempted straight after power-up, even if the FPGA is not programmed.

Two status indicator LEDs are on-board near the RJ-45 connector that indicates traffic (LD10) and valid link-state (LD9). The table below shows the default behavior.

The Genesys 2 includes an FTDI FT232R USB-UART bridge (attached to connector J15) that lets you use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from Windows Update or www.ftdichip.com under the “Virtual Com Port” or VCP heading, convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD) with no handshake signals. After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Y20 and Y23 FPGA pins.

The Pmod connectors are arranged in 2×6 right-angle, 100-mil female connectors that mate with standard 2×6 pin headers. Each 12-pin Pmod connector provides two power pins (6 and 12), two ground pins (5 and 11), and eight logic signals, as shown in Fig. 20. The VCC and Ground pins of can deliver up to 1A of current per pin. Pin assignments for the Pmod I/O connected to the FPGA are shown in.